The present application claims the benefit of Korean Patent Application No. P2001-1627 filed Jan. 11, 2001, which is herein fully incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a flash memory cell array and a method for programming and erasing the flash memory cell array.
2. Background of the Related Art
The most idealistic memory device from a functional perspective is a nonvolatile ferroelectric memory device, which permits a user to optionally switch a memory state electrically so as to facilitate programming and which retains the memory state even in power offs.
Currently, a nonvolatile ferroelectric memory device in view of process technologies includes a floating gate based memory and a Metal Insulator Semiconductor (MIS) based memory having a layered structure of two or more dielectric films.
The floating gate based memory implements memory characteristics using a potential well. An EPROM-Tunnel OXide (ETOX) structure is widely used as a flash Electrically Erasable Programmable ROM (EEPROM).
On the other hand, the MIS based memory performs its memory function using a trap which exists in a dielectric film bulk, a boundary between dielectric films, and a boundary between a dielectric film and a semiconductor layer. A Metal/polysilicon Oxide Nitride Oxide Semiconductor (MONOS/SONOS) structure is mainly used as a full-featured EEPROM.
A related art flash memory cell based on an MIS and a floating gate and a related art method for programming and erasing data using the same will now be described.
FIG. 1 is a structural sectional view of an MONOS/SONOS memory device of a related art MIS based nonvolatile ferroelectric memory device.
As shown in FIG. 1, a first oxide film 12, a nitride film 13, a second oxide film 14, and a gate electrode 15 are sequentially layered on one region of a P-type semiconductor substrate 11. A source region 16 and a drain region 17 are formed within a surface of the semiconductor substrate 11 at both sides of the layered structure.
The first oxide film 12 is used as a tunneling oxide film while the second oxide film 14 is used as a blocking oxide film.
FIG. 2 is a structural sectional view of a memory device having an ETOX structure of a related art floating gate based nonvolatile ferroelectric semiconductor memory device.
As shown in FIG. 2, a tunneling oxide film 22, a floating gate 23, a dielectric film 24, and a control gate 25 are sequentially layered on one region of a P-type semiconductor substrate 21. A source region 26 and a drain region 27 are formed within a surface of the semiconductor substrate 11 at both sides of the layered structure.
The floating gate 23 formed between the tunneling oxide film 22 and the dielectric film 24 is electrically isolated. The control gate 25 formed on the dielectric film 24 on the floating gate 23 acts to switch a memory state by applying a sufficiently great voltage.
The dielectric film 24 between the control gate 25 and the floating gate 23 is an Inter Polysilicon Dielectric (IPD), and the oxide film formed on the semiconductor substrate 21 is the tunneling oxide film 22.
In case where a memory cell having the aforementioned related art ETOX structure is used as a flash EEPROM, a 1-transistor per 1-cell type and a 2-transistor per 1-cell type are used.
The 1-transistor per 1-cell type has a small unit cell area suitable for high packing density and adopts a Channel Hot Electron (CHE) program mechanism having a high program speed. However, the 1-transistor per 1-cell type has a problem in that reliability deteriorates due to over-erasing and disturbance.
To solve a problem related to over-erasing and disturbance, a flash memory cell of a 2-transistor per 1-cell type has been suggested.
FIG. 3 is a structural sectional view of a related art flash memory cell of a 2-transistor per 1-cell type.
As shown in FIG. 3, a MOS transistor 30a and an ETOX memory cell 30b are serially connected with each other at a constant interval on a semiconductor substrate 31. The MOS transistor 30a is used as a selection transistor while the ETOX memory cell 30b is used as a memory transistor.
The process for fabricating the aforementioned related art flash memory cell of FIG. 3 will now be described. First, a first oxide film 32 is formed on a semiconductor substrate 31, and a first polysilicon layer is formed on the first oxide film 32 by a Chemical Vapor Deposition (CVD) method. The first polysilicon layer is removed selectively by photolithography and etching processes to form a floating gate 33.
Subsequently, a second oxide film is formed over the semiconductor substrate 31, and a second polysilicon layer is formed on the second oxide film. The second oxide film and the second polysilicon layer are removed by photolithography and etching processes to simultaneously form a gate insulation film 34a and a dieletric film 34b made of the second oxide film as well as a gate electrode 35a of the MOS transistor and a control gate 35b of the ETOX memory cell made of the second polysilicon layer.
Impurity ions are implanted into an entire surface of the semiconductor substrate 31 using the gate electrode 35a of the MOS transistor and the control gate 35b of the ETOX memory cell as masks to form source regions 36 and a drain region 37 within a surface of the semiconductor substrate 31. Thus, the MOS transistor 30a and the ETOX memory cell 30b are formed serially connected by the drain region 37 on the semiconductor substrate 31.
A related art method for programming and erasing data using a cell array having a unit cell with the configuration of FIG. 3 will be described below.
FIG. 4 is a table showing an operational voltage of the related art flash memory cell having the structure of FIG. 3.
First, a unit cell for programming is selected from a plurality of flash memory cells.
A voltage of xe2x88x928V is applied to a wordline of the selected flash memory cell while 8V is applied to a selection line of the selected flash memory cell. High impedance HiZ is applied to a source 36 while 8V is applied to a drain 37. Also, 0V is applied to a P-well (not shown) while 3.3V is applied to an N-well (not shown).
When performing a programming operation of the selected flash memory cell as above, 0V is applied to a drain, i.e., a bitline so as not to perform a programming operation of other flash memory cells operated by receiving signals of the wordline and the selection line of the selected flash memory cell. This is called a program inhibit operation.
In the programming operation and the program inhibit operation, 0V is applied to wordlines and selection lines of the other flash memory cells to which signals of the wordline and the selection line of the selected flash memory cell are not applied.
In a method for erasing data stored in the related art flash memory cells, 8V is applied to all the wordlines, and 0V is applied to all the selection lines. A voltage of xe2x88x928V is applied to a source while high impedance is applied to a drain (bitline). Also, 0V is applied to a P-well while 3.3V is applied to an N-well.
In a read operation of the related art flash memory cells, 3.3V is respectively applied to a wordline and a selection line of a selected cell. A voltage of 0V is applied to the wordline and selection lines of non-selected cells, a source and a P-well while 1.5V is applied to a drain (bitline).
However, the aforementioned related flash memory cell and the method for programming and erasing data using the same have several problems.
First, the flash memory cell of the 1-transistor per 1-cell type deteriorates reliability due to over-erasing and disturbance. Further, an additional circuit (i.e., the 2-transistor per 1-cell circuit) provided to solve such a problem reduces cell efficiency and results in a complicated design. Moreover, since the flash memory cell of the 2-transistor per 1-cell type has a large cell area per bit, it is difficult to achieve high packing density in related art flash memory cells.
Accordingly, an object of the invention is to solve at least the above problems and/or disadvantages and to provide at least one or more of the advantages as described hereinafter.
Another object of the present invention is to provide a flash memory cell array, which overcomes problems related to over-erasing and disturbance and has a small cell area per bit to obtain high reliability and high packing density.
Still another object of the present invention is to provide a method for programming and erasing data using the flash memory cell array.
To achieve at least these objects and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a flash memory cell array according to one aspect of the present invention includes: a plurality of flash memory cells arranged in a matrix form with a unit cell consisting of a selection transistor of an SONOS structure and a memory transistor of an ETOX structure serially connected with each other; a plurality of selection lines and wordlines arranged in parallel to respectively apply a driving signal to the selection transistor and the memory transistor of the unit cell; a plurality of bitlines respectively contacted between adjacent memory transistors within the same row and arranged in vertical direction to the selection lines; and common source lines respectively contacted between adjacent selection transistors in each row.
In another aspect, in a flash memory cell array which includes a plurality of flash memory cells arranged in a matrix form with a unit cell consisting of a selection transistor and a memory transistor serially connected with each other, a plurality of selection lines connected to a gate of the selection transistor of the unit cell, a plurality of wordlines connected to a gate of the memory transistor of the unit cell, a plurality of bitlines respectively connected to a drain of the unit cell, common source lines commonly connected to a source of the unit cell, and P and N wells formed below each of the flash memory cells, a method for programming data using the flash memory cell array includes the steps of: setting a threshold voltage of the selection transistors at an initial threshold voltage level VT,ref before programming the flash memory cells at N bit data level (level of 2N); selecting a cell for programming among the flash memory cells; and setting a threshold voltage value corresponding to the N bit in the selection transistors so that the memory transistor of the selected flash memory cell is programmed at a constant data value (level) among the N bit data level (level of 2N).
In other aspect, in a flash memory cell array which includes a plurality of flash memory cells arranged in a matrix form with a unit cell consisting of a selection transistor and a memory transistor serially connected with each other, a plurality of selection lines connected to a gate of the selection transistor of the unit cell, a plurality of wordlines connected to a gate of the memory transistor of the unit cell, a plurality of bitlines respectively connected to a drain of the unit cell, common source lines commonly connected to a source of the unit cell, and P and N wells formed below each of the flash memory cells, a method for erasing data using the flash memory cell array includes the steps of: applying a first driving voltage xe2x88x92Vpp4 to all the wordlines; applying a second driving voltage xe2x88x92Vpp3 to the selection lines; and applying a power source voltage Vcc to the source, the drain, the N well, and the P well of the respective cells.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.